| 摘要 |
Circuit includes device coupled to receive a word at its input terminals from an address bus and to gate a rearranged word from its output terminals to a data bus of a controller or processor. The word gated to the data bus has its bits interchanged by coupling each of the input terminals of the device to the output terminals corresponding to the new position of the bit in the rearranged word. The word on the address bus is distinguished from an address by specially coding the high-order lines of the address bus when the lower order lines represent the word.
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