发明名称 |
Elimination of SOI parasitic bipolar effect |
摘要 |
The present invention addresses the foregoing needs by providing a circuit implemented in SOI (silicon on insulator) CMOS, which includes a first node precharged to an activated level, a first transistor coupled between the first node and the second node, a second transistor coupled between the second node and a ground potential, and a third transistor coupled to the second node and operable for preventing the second node from rising to the activated level. The third transistor prevents the parasitic bipolar effect from raising this second node to the activated level. Essentially, the third transistor maintains the second node substantially at a ground level.
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申请公布号 |
US6150834(A) |
申请公布日期 |
2000.11.21 |
申请号 |
US19980190556 |
申请日期 |
1998.11.12 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CIRAULA, MICHAEL KEVIN;DURHAM, CHRISTOPHER MCCALL;KLIM, PETER JUERGEN |
分类号 |
H03K19/003;H03K19/096;(IPC1-7):H03K17/16;H03K19/094 |
主分类号 |
H03K19/003 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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