发明名称 |
DIGITAL SIGNAL PROCESSING SYSTEM |
摘要 |
PROBLEM TO BE SOLVED: To provide a digital signal processing system which can reduce the influence of a communication signal that is caused to an AD-converted signal. SOLUTION: A data communication circuit 2 and AD conversion circuit 3 operate on the basis of the system clocks which are generated by a system clock generation circuit 1. The frequency of communication signal S1 of the circuit 2 is N/2 times as high as the sampling frequency of the circuit 3. The circuit 2 functions to control the phase of the signal S1 so as to set the amplitude of the signal S1 to 0 in a sampling mode of the circuit 3. Thus, it is possible to reduce the influence of the signal S1 that is caused to an AD-converted signal.
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申请公布号 |
JP2000286904(A) |
申请公布日期 |
2000.10.13 |
申请号 |
JP19990089101 |
申请日期 |
1999.03.30 |
申请人 |
MATSUSHITA ELECTRIC WORKS LTD |
发明人 |
MASUDA KOICHI;YAMANE KAZUYASU;SHOJI TAKEMASA |
分类号 |
H03M1/12;H04L27/06;H04L27/22;(IPC1-7):H04L27/06 |
主分类号 |
H03M1/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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