发明名称
摘要 <p>A capacitive load (300) such as the array ground line of a flash memory is initially pulled up towards a positive voltage (350) via a first relatively weak current source (330), and subsequently a stronger source (330,340) is switched to the load. To pull the load down, the pull up sources (330,340) are turned off, and a relatively weak pull-down current source (360,380) switched to the load (300). Subsequently a stronger pull-down source (360,370,380) is switched to the load. The arrangement may avoid high transient currents while ensuring adequate quiescent sourcing ability. <MATH></p>
申请公布号 JP3131555(B2) 申请公布日期 2001.02.05
申请号 JP19950218902 申请日期 1995.08.28
申请人 发明人
分类号 G11C17/00;G11C16/06;G11C16/16;H01L27/10;(IPC1-7):G11C16/06 主分类号 G11C17/00
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