发明名称 |
High speed true/complement driver |
摘要 |
A high speed true/complement driver circuit is disclosed wherein the time interval between the address and memory select pulses are minimized by utilizing a high speed enhancement/depletion mode inverter pair followed by a clocked signal isolation stage. A pair of enhancement mode/depletion mode inverters connected in cascade configuration serves to generate the true and complement output signals which are isolated from noise at the input line by a symmetric pair of clocked FETs.
|
申请公布号 |
US4129793(A) |
申请公布日期 |
1978.12.12 |
申请号 |
US19770807287 |
申请日期 |
1977.06.16 |
申请人 |
IBM CORP |
发明人 |
BULA J;MARTIN L |
分类号 |
H03K5/151;H03K19/0185;H03K19/096;(IPC1-7):H03K17/60;H03K17/16;H03K19/40;G11C8/00 |
主分类号 |
H03K5/151 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|