| 摘要 |
1534230 Shift networks INTERNATIONAL BUSINESS MACHINES CORP 5 Oct 1977 [11 Nov 1976] 41371/77 Heading G4A The shift operations necessary to perform conversions between packed and zoned decimal formats are effected by a routing network which operates in parallel by byte instead of serially by byte as in prior art processors. The routing network is combined with a 0-7 bit shifter in a two-stage network which can perform normal shift operations required in a processor as well as the format conversions. The preferred embodiment of network is formed from integrated circuit chips each of which routes, from each byte, a corresponding bit from the high and low order halves; for example, Fig. 12 shows the chip which handles bit 3 and bit 7 from every byte. This arrangement reduces the number of inter-chip connections which would otherwise benecessary because of the high order-low order cross-overs which occur in the format conversion when the zone codes are inserted or eliminated. Each chip receives a shift amount 47 which is decoded to provide shift control signals R0D-R4 for first and second level byte shifters 50, 53 and 52, 55. The first level normally shifts by between 0 and 3 bytes and the second level by 0 or 4 bytes, a total shift of 8 bytes being performed in the unpack (packedzoned) conversion without sign operation. The second level is also controlled by a control decoder 58 to perform the format conversion shifts which increase/decrease progressively for successive bytes. Fig. 17 shows an example for a zone to packed format conversion for bits 3 and 7 of bytes 0-7. For the reverse conversion, the cross-over is in the reverse direction and 1's are forced in the bit 3 positions of all bytes except that containing the sign digit (byte 6), (the zone code being 1111). An additional chip is provided for handling the byte parity bits. |
