| 摘要 |
A video signal processing circuit for producing a dissolve control signal to control dissolving of a video signal uses primarily digital circuitry to derive the dissolve signal. A phase locked loop is used to produce a clock signal having a frequency which is a multiple of the vertical synchronizing signal in the video signal, and which is frequency divided by a fraction determined by a programmable counter which defines the rate of dissolve. The divided signal is processed by a signal processor and delivered to an up/down counter controlling a digital to analogue converter, the output of which is processed to produce as said control signal a ramp signal of which the slope is determined by the programmable counter. |
