发明名称 |
SRAM cell design for soft error rate immunity |
摘要 |
A new method to form a SRAM memory cell in an integrated circuit device is achieved. The method comprises providing a bi-stable flip-flop cell having a data storage node and a data bar storage node. A first capacitor is formed coupled to the data bar storage node, and a second capacitor is formed coupled to the data storage node. The first and second capacitors comprise a first conductor layer overlying a second conductor layer with a dielectric layer therebetween. One of the first and second conductor layers is coupled to ground. A new SRAM device is disclosed.
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申请公布号 |
US7364961(B2) |
申请公布日期 |
2008.04.29 |
申请号 |
US20050103754 |
申请日期 |
2005.04.12 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
LIAW JHON-JHY |
分类号 |
H01L21/8244;G11C8/02;H01L27/11 |
主分类号 |
H01L21/8244 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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