发明名称 Embedded trap direct tunnel non-volatile memory
摘要 The cell comprises a substrate having a drain region and a source region. An oxynitride layer is formed over the substrate. An embedded trap layer is formed over the oxynitride layer. An injector layer is formed over the embedded trap layer. A high dielectric constant layer is formed over the injector layer. A polysilicon control gate formed over the high dielectric constant layer. The cell can be formed in a planar architecture or a two element, split channel, three-dimensional device. The planar cell is formed with the high dielectric constant layer and the control gate being formed over and substantially around three sides of the embedded trap layer. The split channel device has a source line in the substrate under each trench and a bit line on either side of the trench.
申请公布号 US7365388(B2) 申请公布日期 2008.04.29
申请号 US20050065778 申请日期 2005.02.25
申请人 MICRON TECHNOLOGY, INC. 发明人 BHATTACHARYYA ARUP
分类号 H01L29/792 主分类号 H01L29/792
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