| 摘要 |
<p>STATIC CONTROL FOR STEP VOLTAGE REGULATOR OF THE DISCLOSURE A static control for a step voltage regulator derives a lower bandwidth limit potential at the wiper of a bandwidth setting potentiometer connected across a reference voltage source and an upper bandwidth limit potential at the output of an inverter operational amplifier having inputs coupled to the wiper and to the reference voltage source. First and second comparators respectively compare the upper and lower bandwidth limit potentials to a sample voltage proportional to the regulator output potential. A timer includes a pulse generator for deriving pulses at power line frequency, a digital counter incremented by the pulses, a digital-to-analog network for deriving a unidirectional voltage proportional to the count stored in the counter, and a comparator for providing a timer output when the unidirectional voltage reaches a reference potential. A logic gate normally disables the counter and in response to the output of either comparator to enable the counter and thus start the timer. First and second triggerable semiconductor switches respectively energize the raise and lower windings of the tap changer motor. A latch has crossconnected first and second logic gates respectively controlled by the first and second comparators and each of which receives the timer output and firing pulses from a high frequency oscillator and is enabled when the outputs from the corresponding comparator, the timer, and the oscillator occur simultaneously. Firing circuits controlled by the first and second logic gates of the latch trigger the second and first semiconductor switches to thereby energize the raise and lower windings of the tap changer motor.</p> |
