Low noise precision input stage for analog-to-digital converters

摘要

An input stage to an analog to digital converter (ADC) includes at least one sampling capacitor (SC) for sampling an input signal in acquire phases, a capacitive gain amplifier (CGA) for providing the input signal to the SC, and bandwidth control means. The bandwidth control means is configured to ensure that the SC has a first bandwidth during a first part of an acquire phase and has a second bandwidth during a subsequent, second, part of said acquire phase, the second bandwidth being smaller than the first. In this manner, first, the input signal is sampled at a higher, first, bandwidth allowing to take advantage of using a high-bandwidth CGA to minimize settling error on the SC, and, next, during a second part of the same acquire phase, the input signal is sampled at a lower, second, bandwidth advantageously decreasing noise resulting from the use of a high-bandwidth CGA.

主权项

1. An analog to digital converter (ADC) system comprising:
at least one sampling capacitor configured to sample an input signal in acquire phases; a capacitive gain amplifier (CGA) configured to provide said input signal to said at least one sampling capacitor of an ADC; and bandwidth control means configured to: ensure that the at least one sampling capacitor has a first bandwidth during a first part of an acquire phase, and ensure that the at least one sampling capacitor has a second bandwidth during a second part of said acquire phase, said second part following said first part of said acquire phase, wherein said second bandwidth is smaller than said first bandwidth.