发明名称 Resistive random access memory and manufacturing method thereof
摘要 A resistive random access memory including a substrate, a dielectric layer, and at least one memory cell string is provided. The dielectric layer is disposed on the substrate. The memory cell string includes memory cells and at least one first interconnect structure. The memory cells are vertically and adjacently disposed in the dielectric layer, and each memory cells includes a first conductive line, a second conductive line, and a variable resistance structure. The second conductive line is disposed at one side of the first conductive line, and the top surface of the second conductive line is higher than the top surface of the first conductive line. The variable resistance structure is disposed between the first conductive line and the second conductive line. The variable resistance structures in the vertically adjacent memory cells are isolated from each other. The first interconnect structure is connected to the vertically adjacent first conductive lines.
申请公布号 US9391271(B1) 申请公布日期 2016.07.12
申请号 US201514670429 申请日期 2015.03.27
申请人 Powerchip Technology Corporation 发明人 Hsu Mao-Teng;Huang Chiu-Tsung
分类号 H01L29/80;H01L21/00;H01L21/337;H01L45/00;H01L27/24 主分类号 H01L29/80
代理机构 Jianq Chyun IP Office 代理人 Jianq Chyun IP Office
主权项 1. A resistive random access memory, comprising: a substrate; a dielectric layer disposed on the substrate; and at least one memory cell string, comprising: a plurality of memory cells, wherein the memory cells are vertically and adjacently disposed in the dielectric layer, and each of the memory cells comprises: a first conductive line;a second conductive line disposed at one side of the first conductive line, and a top surface of the second conductive line is higher than a top surface of the first conductive line; anda variable resistance structure disposed between the first conductive line and the second conductive line, whereinthe variable resistance structures in the vertically adjacent memory cells are isolated from each other; andat least one first interconnect structure connected to the vertically adjacent first conductive lines.
地址 Hsinchu TW