发明名称 MULTIPLE PHASE CLOCK GENERATOR
摘要 <p>MULTIPLE PHASE CLOCK GENERATOR A two phase clock signal with separation between the two phases is produced from a single phase clock. Two complementary input signals are derived from the single phase clock and are transferred by separate transfer gates to individual push/pull amplifiers. Each gated input signal is applied to the first input of one of the amplifiers while the complementary input signals are connected directly to the second input of the amplifiers. The output of each push/pull amplifier is one of the clock phases, and each is also applied to a sensing circuit. The sensing circuit produces delayed outputs which are cross-coupled to control the transfer gate associated with the other output phase. By judicious selection of the parameters of the sensing circuit, the time and speed of "turn-on" for each transfer gate can be controlled. Accordingly, the separation between the two clock phases as well as the shape of each can be selected.</p>
申请公布号 CA1041615(A) 申请公布日期 1978.10.31
申请号 CA19760249019 申请日期 1976.03.29
申请人 TELETYPE CORPORATION 发明人 ALVAREZ, CESAR E. (JR.)
分类号 G06F1/06;H03K5/151;(IPC1-7):03K1/17;03B27/00 主分类号 G06F1/06
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