发明名称 INSPECTION SYSTEM FOR SEMICONDUCTOR MEMORY
摘要 <p>PURPOSE:To speed up the inspection, by applying the input signal pattern being the chip disable with high speed, by checking whether the voltage at the data output terminal at that time is within a given range or not, and by confirming the disable function with the operation speed of device.</p>
申请公布号 JPS53124931(A) 申请公布日期 1978.10.31
申请号 JP19770039504 申请日期 1977.04.08
申请人 HITACHI LTD 发明人 MIWA AKIO
分类号 G11C17/00;G01R31/26;G01R31/28;G11C7/24;G11C29/00;G11C29/56 主分类号 G11C17/00
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