| 摘要 |
PHD.77-029 28-2-1978 In electronic computer systems peripheral units are generally connected in series to the central processing unit via a common data bus. Via the data bus the data signals of one specific sign and, as the case may be, control signals are each time transmitted with a parallel clock signal, whose instant of appearance indicates when the other signals are valid. All signals in each peripheral unit pass through the same number of circuit elements, in particular regeneration amplifiers and logic circuits, a plurality of circuit elements being each time combined in one integrated semiconductor circuit, which may exhibit different propagation delays. In order to ensure that also in a longer chain of peripheral units the clock signal neither appears before the data signal with the greatest delay nor unnecessarily later so as to obtain the maximum transmission speed, the clock signal in each peripheral unit is in addition passed in parallel through all integrated semiconductor circuits and at the output of said circuits combined in such a way that the active state does not appear prior to said state at the output of the semiconductor circuit, or semiconductor circuits, with the greatest delay. Thus, the clock signal is always delayed to at least the same extent as the data signal with the greatest delay, for which some additional circuit elements must be included in each peripheral unit. |
