发明名称 |
Digital logic level signal indication of phase and frequency lock condition in a phase-locked loop |
摘要 |
A digital logic level signal indicates whether a first signal in a phase-locked loop is locked in phase and frequency with a second signal provided to the loop. The digital logic level signal is provided from the sequentially last stage of a counter having a predetermined number of stages. The counter counts cycles in an input signal corresponding to one of the first signal and the second signal. A reset signal pulse having a first predetermined duration is provided to the counter from a pulse width discriminator when the pulse width discriminator detects a phase difference between the first and second signals of greater than a second predetermined duration. The reset signal pulse resets the counter. The digital logic level signal is in a state indicating an in-lock condition when a predetermined number of input signal cycles occur without the counter being reset.
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申请公布号 |
US4122405(A) |
申请公布日期 |
1978.10.24 |
申请号 |
US19770844409 |
申请日期 |
1977.10.21 |
申请人 |
NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
TIETZ, GARY WILLIAM;MUELLER, KEITH JAMES |
分类号 |
H03K5/26;H03L7/089;H03L7/095;(IPC1-7):H03D3/04;H03K5/20 |
主分类号 |
H03K5/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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