| 摘要 |
A method and apparatus are described for generating a sequence of signals using first and second read-only memories, a counter associated with each memory as an address register, a source of timing signals connected to the input of each counter, decoding apparatus for the output of each memory and control logic to enable only one memory at a time. The two memories are organized in hierarchical fashion so that the first memory controls the second. Advantageously, the first memory provides for generation of unique portions of the sequence while the second memory provides for generation of repeated portions of the sequence.
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