发明名称 Receiver for DC signals - has threshold cct. with two thresholds inserted into subscriber line
摘要 <p>The first threshold of the receiver is close to the spacing current between two signal bits, and the other threshold is near the bit amplitude value. A timing generator is switched on by the bit falling flank, both when it falls below the first threshold, and by its rising flank when it exceeds the second threshold. After an adjustable protective time interval has elapsed, the generator transmits a clock pulse to an output circuit prepared by an input circuit controlled by the threshold circuit signals. Received distorted d.c. signals can be evaluated widely free of distortion.</p>
申请公布号 IT1026613(B) 申请公布日期 1978.10.20
申请号 IT19740029951 申请日期 1974.11.28
申请人 SIEMENS AG 发明人
分类号 H03K17/16;H03K17/28;H03K17/30;H04B;H04B1/16;H04L;H04L17/18;H04L25/06;(IPC1-7):04B/ 主分类号 H03K17/16
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