SELF-ALIGNED CMOS PROCESS FOR INSULATING SUBSTRATE DEVICE

摘要

1529296 CMOS devices NATIONAL SEMICONDUCTOR CORP 6 May 1976 [8 May 1975] 42667/77 Divided out of 1529023 Heading H1K In the manufacture of a CMOS structure an N-type Si layer 13 is first deposited on an insulating substrate 13, e.g. of sapphire or spinel, oxide 33 and nitride 34 layers are sequentially formed thereon, P + -type source and drain regions 35 are diffused through openings etched in the layers 33, 34 during which diffusion thick oxide 36 forms on the regions 35, a mask 37 is applied over parts of each of the thick oxide layers 36 and over the intervening N-type channel region 351, and a thin P- channel-forming zone 39 is formed, preferably by ion implantation (Fig. 5). The exposed oxide 36 and the underlying semiconductor material are then etched away to leave two discrete semi-conductor islands on the substrate 32, the edges of the islands are oxidized during which heating step the P- dopant from zone 39 is driven-in, openings are formed over the right hand island and source and drain regions 42 are diffused therein, the remaining nitride 34 is removed from over the two gate regions and, following opening of appropriate contact holes, source, drain and gate metallization 44, 45 is deposited and defined.