| 摘要 |
<p>A circuit arrangement for facilitating the transmission of asynchronously occurring binary data values is described. Each binary value change is assigned a multibit pulse group in the frame of a coarse scanning pulse train. A pulse discriminator, upon the occurrence of a binary value change and upon the arrival of a scanning signal, emits a writein command which causes the pulse group to be placed in a register. A counter is provided for counting the number of coarse scanning pulses occurring from the time of occurrence of the write-in command. Prior to reaching a predetermined count, the counter blocks further write-in commands, and after reaching the predetermined count, the write-in commands are released. Thus, a correctly formed pulse group is emitted even though the received binary values might be distorted.</p> |
