| 摘要 |
<p>A digital vertical deflection rate synchronization system includes a source of clock pulses which drives a divide-by-525 counter and a serial-to-parallel shift register. An incoming low frequency signal such as that obtained from the sync separator stage of a television receiver is scanned at the clock rate to determine whether it exhibits the width characteristic of the vertical sync signal. If the incoming signal does not, the vertical deflection sawtooth generator is synchronized by a pulse derived from the divide-by-525 counter. If the incoming signal does exhibit the vertical sync pulse width characteristic, it is allowed to reset the divide-by-525 counter. In the event that the divide-by-525 counter is reset before it has passed a synchronizing pulse to the vertical deflection sawtooth generator, an overscan limit control circuit senses the collapsing vertical deflection synchronizing pulse.</p> |
