发明名称 |
Circuit arrangement for controlling the pulse repetition frequency of a signal |
摘要 |
A circuit arrangement is described wherein the pulse repetition frequency of a signal is digitally controlled in dependence on the pulse repetition frequency of a controlling signal. A presettable digital counter functioning as a frequency divider operates between preset initial and end counts and is reset to the initial value each time the end value is reached; the initial and end values are set responsive to binary signals applied to control inputs of the counter. A bistable trigger stage assumes either an idle or an operative state in dependence on the value of a control signal derived from the controlling pulse repetition frequency and a timing signal. The trigger stage output is used to control either the setting of the afore-mentioned initial value or the end value to produce either too high or too low values for the pulse repetition frequency of the controlled signal.
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申请公布号 |
US4115687(A) |
申请公布日期 |
1978.09.19 |
申请号 |
US19770786214 |
申请日期 |
1977.04.11 |
申请人 |
SIEMENS AKTIENGESELLSCHAFT |
发明人 |
BOESE, GUNTER;NEUDORFER, ERNST;SCHOLLMEIER, GERO |
分类号 |
H03K5/00;G06F7/68;H03K21/38;H03K23/66;H03L7/099;H04L27/00;(IPC1-7):H03K21/36 |
主分类号 |
H03K5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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