发明名称 WERKWIJZE VOOR HET VERVAARDIGEN VAN EEN GEINTEGREERDE HALFGELEIDERSCHAKELING.
摘要 In a method of making integrated circuits, prior to vapor deposition of metal layers on an insulating layer for interconnection, each opening on the insulating layer is filled with an embedded metal layer in order to smoothen the surface to be vapor deposited and to avoid undesirable thin parts of the vapor deposited metal layer at the step between the lower part in the opening and the elevated part on the insulating layer. The filling of the embedded metal layer in each opening is made by a first step of coating a metal layer on the whole surface of the principal face of the semi-conductor, which surface is coated by the insulating layer with specified openings and further by a photoresist layer which has been used for etching the insulating layer to form said openings and is left covering said insulating layer, and by the subsequent step of applying a photoresist removing liquid on the face to remove the photoresist layer and the part of metal layer still remaining on the photoresist layer.
申请公布号 NL158026(B) 申请公布日期 1978.09.15
申请号 NL19730014156 申请日期 1973.10.15
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., KADOMA, JAPAN. 发明人
分类号 H01L21/28;H01L21/027;H01L21/285;H01L23/29;H01L23/522;(IPC1-7):01L21/72;01L29/78 主分类号 H01L21/28
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