Depletion/enhancement mode FET logic circuit

摘要

Disclosed is a field effect transistor (FET) logic circuit which advantageously combines enhancement and depletion mode field effect transistors. A depletion mode input transistor is connected between an input node and an intermediate node and has its gating electrode connected to a fixed potential such as ground. A self-biased depletion mode field effect load transistor is connected between a positive potential and the same intermediate node to which the gating electrode of one or more enhancement mode field effect transistors are also connected. The source electrodes of the enhancement mode field effect transistors are connected to a fixed source of potential such as ground while the drain electrodes of the enhancement mode field effect transistors provide open drain outputs to similarly constructed subsequent logic stages. A number of these open drain logic outputs may be connected together to form DOT logic configurations and the potential swing at these open drain outputs, being a function of the threshold voltage of the subsequent stage input device, is substantially less than the potential difference between the fixed positive and ground supply potentials.