Random access memory with memory status for improved access and cycle times

摘要

A static random access memory which generates a memory status signal for improved performance. The same signal in a random access memory which enables data to go to the output is taken to form the leading edge of a memory status signal, indicating that output data is available. The trailing edge of the pulse, indicating a memory readiness condition, is formed upon completion of memory preset. The memory status signal tracks variations in performance of the data storage cells due to voltage, temperature and other processing variables, thus permitting access of data when data is actually available for reading, rather than on worst case considerations.