FAULT-TOLERANT COMPUTER SYSTEM FITTED WITH MULTIPROCESSOR

摘要

PURPOSE: To prevent the synchronizing operation from being extremely drifted away by providing an interrupt circuit which responds to the count selected in each of all counters. CONSTITUTION: A cycle counter 71 is so set that it overflows at one point before expiration of a maximum interrupt latency period. An interrupt synchronizing request signal and an interrupt signal are generated by the overflow to force resynchronization. When a processor 40 supplies an interrupt, a code in an interrupt routine forces the occurrence of an event. The synchronizing request signal internally generated in this manner causes resynchronization with the event generated by the interrupt routine.