发明名称 OUTPUT BUFFER CIRCUIT FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To suppress overshoot and undershoot of an output waveform and to drive an output load at high speed by devising the title circuit such that a load drive capability of an output buffer circuit is adjusted stepwise in response to the level of an output signal. CONSTITUTION:P-channel MOS transistors(TRs) P12 and P13 are connected in parallel with a P-channel MOS TRs P11, and N-channel MOS TRs N12 and N13 are connected in parallel with an N-channel MOS TR N11. The MOS TRs are subject in stepwise to control for energizing so that lots of MOS TRs in the early period of the leading or trailing edge period (transit period) of an output signal O1 and a few of MOS TRs in the latter period contribute to the drive of an output load. Thus, the production of overshoot and undershoot of an output waveform is prevented, and the output load is driven at high speed.
申请公布号 JPH02206913(A) 申请公布日期 1990.08.16
申请号 JP19890028058 申请日期 1989.02.07
申请人 NEC CORP 发明人 WABUKA YUTAKA
分类号 H03K17/04;H03K17/687;H03K19/0185;H03K19/0948 主分类号 H03K17/04
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