| 摘要 |
1520604 Electronic timepieces TOKYO SHIBAURA ELECTRIC CO Ltd 28 April 1976 [28 April 1975] 17237/76 Heading G3T An electronic timepiece has a time setting and displaying mode control circuit 7, Fig. 1, which supplies display mode signals to a decoder 8 to display the content of selected counters 2-6, and which to effect time correction supplies setting mode signals SZ, MIS, HS, DS, MOS to a selected one of the counters to correct only that counter. The circuit 7 includes two switches to selectively cause one of the time setting or time display mode signals in accordance with the number of times the switches are each successively operated and in dependence upon whether a switch is maintained closed for two or more seconds. Detection circuits detect operation of respective switches and respective ring counters memorize the state thereof to effect through logic circuits the selected mode. In Figs. 2A, 2B, a detection circuit 10 comprising shift registeres 11-13 and 15,16 detects the state of switch SW1. Likewise a detection circuit 50 comprising shift registers 51- 53 and 55, 56 detects the state of SW2. A pulse is produced from NOR gate 14 each time SW1 is depressed. Similarly a pulse is produced from NOR gate 54 each time SW2 is depressed. A NOR gate 40 produces a pulse when SW1 is maintained closed for two or more seconds; a NOR gate 59 passes a 1HZ signal when SW2 is maintained closed for two or more seconds. A time setting mode circuit 30 includes a ring counter comprising shift registers 31-34 and a NOR gate 35. A time displaying mode circuit 60 includes a ring counter formed by shift registers 61, 62 and a NOR gate 63. Setting Mode Successive depressions of switch SW 1 shifts the content of registers 31-34 so that a logic "1" appears at the output of each register in turn and is supplied as an hour, minute, month or date setting mode signal to respective counters 4, 3, 6, 5. During time setting, the ring counter 61, 62 is reset by the output of NOR gate 35, and, if SW2 is depressed for two or more seconds, a 1HZ pulse train is passed by an AND gate 58 and via NOR gates 59, 43, AND gates 36, 37, 38 or 39 to counter 4, 3, 6 or 5 thereby to advance the respective counter. Display Mode If SW1 is maintained closed for two or more seconds, the shift registers 31-34 will be reset via AND 17 or NOR gate 40, irrespective of the mode pertaining, and the hours/minutes display mode will be established. If SW2 is now depressed, the output from AND gate 42 shifts the content of registers 61, 62 so that a "1" output from 61 is passed via AND gate 65 to decoder 8 to cause a month/date display. If SW2 is depressed again the output from 62 via AND gate 66 causes a seconds display. A further depression of SW2 results in change-over to the hours/minutes display. |
