High speed dynamic flip-flop system

摘要

A high speed dynamic CMOS flip-flop system having a master and a slave section each of which have a different total propagation delay. Asymmetrical clock signals are applied to the master and slave sections with one cycle portion of each clock signal turning on the master section and the other cycle turning on the slave section. Each cycle portion has a time duration substantially equal to the total propagation delay of its respective master and slave section. In this manner, the duty cycle of the clock signal cycle is matched to the ratio of the propagation delays of the master and slave sections.