| 发明名称 |
DIGITAL PHASE SYNCHRONIZING LOOP |
| 摘要 |
PURPOSE:To obtain the phase locked loop which can reduce the capacity of ROM to around 1/4 without increasing the zitter of the output, by skillfully setting the relation between the phase and the address of ROM through the constitution of the sinusoidal wave oscillator with ROM. |
| 申请公布号 |
JPS5389348(A) |
申请公布日期 |
1978.08.05 |
| 申请号 |
JP19770003610 |
申请日期 |
1977.01.18 |
| 申请人 |
TOKYO SHIBAURA ELECTRIC CO |
发明人 |
YAHATA MEIKI;YODA SHIYUNSUKE;KAWASAKI TADAMICHI |
| 分类号 |
H03B28/00;H03D1/22;H03J5/00;H03L7/00;H03L7/06 |
主分类号 |
H03B28/00 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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