| 摘要 |
1376268 Digital data processors PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 8 Jan 1973 [11 Jan 1972] 955/73 Heading G4A A computer comprises a central processor E and optionally an auxiliary processor A. Operations are executed on an address associated with an instruction received from a store MEM. If the auxiliary processor is present and operative the address is processed in it, but if it is not the processing takes place in the arithmetic unit of the central processor. When clock unit CL gives a signal control unit CBE reads out and increments program counter PC. The command from PC passes via unit CAC to store MEM where it reads out an instruction word from the corresponding storage position. The instruction word passes over line OL2 to registers OPC and OPAD which respectively store the instruction code and operand address portions of the instruction. The instruction can not pass direct to registers OPS, ADS because unit BLOC is blocked if the auxiliary processor A is operative. The address is processed in ADB and passes to address register ADS. The instruction code is checked for parity, &c., in INT. This unit INT also includes an address counter which blocks unit CBE until the end of a series of addresses implicit in the instruction word is reached. The unit INT is connected to instruction register OPS. The processed address in ADS passes to the store MEM which provides an operand from the corresponding address to operand register ORS. Control unit CBE now causes arithmetic unit RE to request the instruction from OPS and the operand from ORS, and to execute the instruction on the operand. Auxiliary processor is now available for a further sequence of operations, and so the next instruction and operand may be available for execution by RE at the instant that RE has completed the preceding execution, i.e. look ahead facility is present. The result of each execution in RE passes to store MEM via register ORS2. If processor A is absent or inoperative the arithmetic unit RE of processor E processes the instruction word read from MEM under the control of a command signal from RE on line CL1, unit BLOC now being unblocked. The instruction passes to OPS and ADS. The address portion is processed in RE and returned to ADS to select the operand from MEM. Unit RE also processes the instruction code from OPS and performs the necessary operations on the selected operand, the result passing to MEM via ORS 2. |
