RANDOM ACCESS MEMORY SYSTEM AND CELL

摘要

In an array of memory cells having the cells in each column coupled together by one of a plurality of address buses, the ground reference potential for each cell is provided by coupling a storage capacitor in each cell to an adjacent address bus. Since only one address bus is addressed at any selected time, the adjacent address buses remain at ground potential so that coupling of the storage capacitors in each addressed cell to the adjacent, grounded address buses supplies the required reference ground for each addressed cell. Refreshing, or restoring of the charges on the storage capacitor in each memory cell is accomplished by a plurality of sense-refresh amplifiers. Each sense-refresh amplifier can be coupled to a selected cell capacitor in a row of memory cells, and includes a first pair of MOSFET devices cross-coupled in a flip-flop configuration. In one embodiment, single phase clock signals are applied to the first pair of MOSFET's through an ON biased second pair of MOSFET's. The clock signals thus applied synchronize the read, write, and refresh functions of the memory. Alternatively, single phase clock signals can be applied to a third pair of MOSFET's coupled in parallel with the first pair, or a clock pulse can be used to short a pair of circuit nodes during an initial time period to bring a pair of load capacitances to a desired, low initial potential. Data signals are applied to and read-out from only one side of the sense-refresh amplifier, and the sense-refresh amplifier also serves to invert the data stored in memory cells on the opposite side, and to re-invert the data on read out.