| 摘要 |
<p>A digital timing circuit comprising integrated circuits is presented for multifrequency signal receivers in which a first counter is pulsed by a clock to generate predetermined timing intervals under the control of a second counter. The second counter sequentially recycles the first counter to make multiple use of the stages therein to provide various timing intervals, each associated with a timing function, e.g., initial state and signal persistence timing, fixed duration output pulse, signal check and delayed steering release. Multiple use of the first counter by the second counter provides efficient use of the first counter and reduces size and cost of the circuit.</p> |
