发明名称 SIGNAL MONITORING CIRCUIT
摘要 Signals such as track signals in a railway signalling system are monitored by antiphase sequential application to an enabling input of a control circuit which starts the operation of a timer, providing an output signal only if the control circuit is enabled for a time interval during which all the signals being monitored are present sequentially. Absence of any one of the signals in this interval results in a fail-safe condition, resetting the timer, which then fails to provide an output. In the application to a railway signal monitoring system absence of any one signal would be indicative of occupation of an associated track section, resulting in a 'danger' condition being signalled.
申请公布号 AU2142777(A) 申请公布日期 1978.07.27
申请号 AU19770021427 申请日期 1977.01.19
申请人 M.L. ENGINEERING (PLYMOUTH) LTD. 发明人 ERNEST JAMES MOOREY
分类号 B61L1/18;H03K5/26 主分类号 B61L1/18
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