发明名称 Collision avoidance system for model railways - uses programmable memory with integrated circuit logic module for points setting
摘要 <p>The anti-collision signalling system for railway networks, esp. model railway layouts comprises a monitor associated with each set of points at the start or end of a length of track. The set position of these points provides a blocking signal for all other track sections associated with this set of points. The monitor is constructed from an integrated circuit logic module. A programmable memory is used to store the information relating to the straight or branch line settings associated with the sets of points to be traversed. The outputs of the memory give either logic high or logic low signals depending on whether the points are to be set for a straight-through or branching operation on a certain track length.</p>
申请公布号 DE2702630(A1) 申请公布日期 1978.07.27
申请号 DE19772702630 申请日期 1977.01.22
申请人 JAEGER,ANDREAS 发明人 JAEGER,ANDREAS
分类号 B61L21/04;(IPC1-7):61L21/04 主分类号 B61L21/04
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