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经营范围
发明名称
MULTILEVEL LOGIC CIRCUIT
摘要
PURPOSE:To simplify the circuit constitution by connecting a plural number of non-linear loads to one FET or bipolar transistor.
申请公布号
JPS5384649(A)
申请公布日期
1978.07.26
申请号
JP19760160640
申请日期
1976.12.29
申请人
FUJITSU LTD
发明人
SUYAMA KATSUHIKO
分类号
H03M1/36;H03K19/094;H03K19/20
主分类号
H03M1/36
代理机构
代理人
主权项
地址
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