发明名称 KOPPLINGSANORDNING FOR INLESNING OCH UTLESNING AV SIGNALER I RESP UR ETT MINNE
摘要 1486912 Data storage; analogue-to-digital and digital-to-analogue conversion SIEMENS AG 26 Sept 1974 [28 Sept 1973] 41841/74 Heading H3H To economize on storage capacity, a group of digital signals Be1-Be3 are combined and the combination converted to an analogue signal which is stored in a selected address of a capacitor matrix store Sp, the individual digital signals being recovered at Ba1-Ba3 on read-out. Digital-to-analogue conversion.-Decoder Db enables an appropriate one of F.E.T. gates T1-Tn to connect a respective one of a set of mutually different voltage sources U1-Un to a storage capacitor C1-Cn selected by an address decoder Da in accordance with signals applied to Se1-Se3. Analogue-to-digital conversion.-The voltage on a storage capacitor C1-Cn selected by signals applied to Le1-Le3 is compared by a comparator Vgl with the voltage sources U1-Un selected in turn by the output of a counter Z incremented by a pulse generator TG, incrementing being discontinued when the comparator senses equality, the counter then being read out via S3-S5 to deliver the corresponding group of digital signals Ba1-Ba3. The counter Z is reset to zero at the start of each read-out by a signal received via OR gate GO2 and pulse former Rs. The read-out circuit may be completely separate from the write-in circuit.
申请公布号 SE402998(B) 申请公布日期 1978.07.24
申请号 SE19740012226 申请日期 1974.09.27
申请人 * SIEMENS AG 发明人 E * ZWACK
分类号 G11C11/404;G11C11/4096;G11C11/56;(IPC1-7):11C7/00;11C27/00 主分类号 G11C11/404
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