| 摘要 |
A phase locked circuit according to the present invention includes means for multiplying a signal to be phase locked by an integer N. A resettable divide counter divides the multiplied signal by N for return to a phase comparator. Reset means operates the resettable counter upon command so that when the input signal to the phase locking circuit is changed (i.e., between two signals each having approximately the same frequency but which may be out of phase), the reset means is operated to reset the divide counter so that the maximum phase error if the signal delivered to the phase comparator is pi /N radians. |
