| 摘要 |
1,010,179. Electric digital computers. RADIO CORPORATION OF AMERICA. Nov. 22, 1962 [Dec. 4, 1961], No. 44249/62. Heading G4A. A data processing system includes a basic data processing system having an instruction register and an instruction decoder, and a supplemental data processing system having an instruction decoder responsive to words in the basic system instruction register, control of operations for the entire system being transferred to the supplemental instruction decoder when an instruction is decoded thereby. A flexible system comprising a basic system to which a variable number of supplemental systems may be added is thus provided, the supplemental systems being capable of performing additional operations or of overriding certain of the basic system operations. Basic system.-A basic system Sa, Fig. 3, includes a memory 300 and an instruction register 10a, the contents of the operations portion of which is referred to as an " operations word ". In the basic system 8a, an instruction decoder 12a applies signals to a machine instruction generator 18a which produces a sequence of signals for each operations word, each of these signals causing a bit pattern generator 20a to produce a sequence of bit patterns which are applied to a bit pattern register 22. The output of the register 22 is applied to a bit pattern decoder 24 which produces one or more command signals for each bit pattern, the command signals being applied to the arithmetic unit and other networks 23 in the basic system. When a circuit which has received a command completes its function, it produces an output signal, called a " return ", which is applied to " return " sensing circuit 27 which produces outputs to clear the bit pattern register 22 thereby causing the bit pattern generator 20a to apply a new pattern to the register 22. Supplemental systems.-To the basic system 8a, there may be added one or more additional systems 8b. The system 8b contains an instruction decoder 12b responsive to certain operations words in the instruction register 10a and connected to a machine instruction generator 18b whose output is applied to a bit pattern generator 20b connected to the bit pattern register 22 in the basic system 8a, thereby producing command signals via the decoder 24 for the arithmetic units and other networks 23, 23b, 23c in any supplemental systems which are connected to the basic system. When the instruction decoder 12b is activated it causes inhibit circuits 31b to inhibit the machine instruction generator 18a in the basic system. Circuit details.-The circuits in each system for the machine instruction generator, bit pattern generator, bit pattern register and bit pattern decoder, which consist of arrangements of gates and flip-flops, are described in detail in the Specification (Figs. 6-8, not shown). |
