INTERLOCKING SYSTEM FOR COMPUTOR CONTROLLING OUTPUT,申请号JP19760152881-传众专利搜索

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发明名称	INTERLOCKING SYSTEM FOR COMPUTOR CONTROLLING OUTPUT
摘要
申请公布号	JPS5377979(A)	申请公布日期	1978.07.10
申请号	JP19760152881	申请日期	1976.12.21
申请人	TOKYO SHIBAURA ELECTRIC CO	发明人	NOGUCHI MASAYA;HAYATO SABUROU;SHIMAMURA HIROSHI
分类号	G05B9/02;G05B15/02	主分类号	G05B9/02
代理机构		代理人
主权项
地址

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