| 摘要 |
A table translator circuit arrangement comprises a plurality of random access word organized memories, input circuitry, output circuitry, and control circuitry. The word locations of each memory are separated into control and data locations defined by corresponding ranges of memory access addresses. Each table entry comprises one or more access control bits and associated data. Each table address defines a control location in one memory of the plurality and data locations in additional memories of the plurality. An entry to be written into the table is provided to input rotate circuitry which is controlled by a portion of the table address which defines the location at which the entry is to be written. The input rotate circuitry delivers the access control bits of the entry to a memory in which a control location is accessed and delivers the associated data bits to additional memories in which data locations are accessed. When an entry is read from the table, the address corresponding to that entry is utilized to access the control and data locations containing the entry. An entry read from the table is provided to output rotate circuitry which is controlled by a portion of the table address which defines the location from which the entry is read. The output rotate circuitry reassociates the access control bits and the associated data bits to their original format. To rapidly clear the memory locations which can contain access control bits, all memory addresses which define control locations are sequentially accessed in parallel in all memories of the plurality. An address generator which defines the memory addresses at which control bits can be stored is stepped sequentially through those addresses and as each address is utilized, the control bits at those locations are cleared. Accordingly, a control location is simultaneously cleared in each of the memories of the plurality thereby dividing by the number of memories the time necessary to clear the table locations which can contain access control bits.
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