Transmission error recognition circuit - suppresses code words recognised as erroneous in PCM transmission system using set of comparators in parallel

摘要

A circuit is used for the recognition on reception of m possible codewords in a redundant code of n bits, with a maximum of p transmission errors. It is used especially for the recognition of clock matching information in plesiochronous PCM pulse sequences. A set of m paralleled comparators (2) is provided which compared received sequence simultaneously and bit for bit with the m possible codewords, formed in a pattern generator (1) and which are connected to m memory units (3) which add the non-agreements detected in the comparators. The memory outputs are connected to a logic circuit (5) which identifies memories showing less than p+1 disagreements, giving an output to the 'correct' channel (a, e) but giving no output if more than p errors are registered.