发明名称 SYSTEM FOR ANALYZING AND PROCESSING HIGH LEVEL DATA LINK CONTROL SEQUENCE FRAME
摘要 PURPOSE: To avoid remarkable increase of same hardware means of each channel by receiving an HDLC frame common in all channels and supplying a receiving word composed of a data byte and status information connecting with this byte for each PCM channel in the form of frame. CONSTITUTION: An HDLC decoding means 70 removes an HDLC envelope from the data received from a PCM link and supplies usable data at a speed of one information item per interval. The data supplied to a FIFO 73 is read by a word analysis/process means 74, and information to manage an appropriate processing of received presence data 71 together with information on the state of a PCM channel (INF) and the rank of presence bytes in a presence frame (ROC).
申请公布号 JPH02226943(A) 申请公布日期 1990.09.10
申请号 JP19890338020 申请日期 1989.12.26
申请人 ALCATEL NV 发明人 FUABURISU BERUNARUDEIINI
分类号 H04L29/08;H04J3/00;H04J3/16;H04L5/22;H04L29/06 主分类号 H04L29/08
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