| 摘要 |
1,259,178. Pulse discriminating circuits. BURROUGHS CORP. 12 Aug., 1969 [30 Aug., 1968], No. 40164/69. Heading H3P. A pulse discriminating circuit, e.g. for recovery of binary data stored as NRZ pulses on magnetic tape, disc or drum, has provision for detecting low amplitude pulses (A at t2) lying between pulses of opposite polarity but not responding to low amplitude noise pulses (A at t4) not followed by a pulse of opposite polarity. As shown, signals A from a reading head 1 are amplified at 2 and fed to positive and negative threshold detectors 3, 5 giving waveforms D, C. A peak detector 4 gives a change in output (B) in response to each input peak. A bistable chain 14, 16, 18 is set by each coincidence of waveforms B, D and reset by each coincidence of waveforms B, C. Each time a pulse exceeding the threshold occurs, one of monostable multivibrators 8 or 9 produces an enabling signal for AND gates 10 or 11 that lasts for 1À5 bit periods (E, F). A second bistable chain 15, 17, 19 is arranged to change state in response to each threshold bit and also in response to each peak occurring in a time slot following a threshold bit. JK flip-flops 16...19 are arranged to step the states of circuits 14, 15 following each clock pulse I from source 20. A logic circuit 72 is arranged to couple the output of one of flip-flops 18, 19 to output N if the states of the bi-stable channels agree and, if the states of the channels fail to agree, to couple the second channel M to the output N. An interlock circuit 73 prevents the generation of more than one pulse following each required input signal. Modifications.-The clock pulses may be derived from the data. Different threshold levels may be provided for the first and second time slots following a threshold signal. |
