发明名称 |
MNOS memory transistor having a redeposited silicon nitride gate dielectric |
摘要 |
A processing technique utilizing two separate silicon nitride depositions (one to form the memory regions and the second to form the nonmemory regions) is employed to provide a radiation hard drain source protected memory transistor. The amount of silicon dioxide used in the nonmemory regions is also minimized. A typical device comprises a mesa etched from a silicon-on-sapphire (SOS) wafer into which P+ source and drain regions are implanted. A 100 A layer of silicon dioxide and a second 1000 A layer of nonmemory silicon nitride covers the mesa and the two layers are etched to define a substrate gate window. The gate window is covered by a 25 A layer of tunneling oxide A final 500 A layer of memory silicon nitride covers the mesa structure. Contact windows are etched to accommodate source, drain and gate interconnect electrodes.
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申请公布号 |
US4096509(A) |
申请公布日期 |
1978.06.20 |
申请号 |
US19760707574 |
申请日期 |
1976.07.22 |
申请人 |
THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE AIR FORCE |
发明人 |
BLAHA, FRANKLYN C.;CRICCHI, JAMES R. |
分类号 |
H01L21/86;H01L29/49;H01L29/51;H01L29/786;H01L29/792;(IPC1-7):H01L29/78;H01L29/34;H01L27/02 |
主分类号 |
H01L21/86 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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