Subchannel memory access control system

摘要

A subchannel memory access control system for use in a data processing system having multiplexor channels to which input/output control units of a first group are connected, and block multiplexor channels to which input/output control units of second and third groups are connected. A plurality of input/output devices of corresponding groups are connected to each control unit. The subchannel memory comprises unit control word memory domains corresponding on a one-to-one basis to the input/output devices of the first group; a pool of unit control word memory domains for use by each operational input/output device connected to an input/output control unit of the second group, to be unshared and dedicated to its respective input/output device; unit control word memory domains of the third group corresponding on a one-to-one basis to each of the input/output control units of the third group, each unit control word memory domain to be shared or utilized in common by the plurality of input/output devices controlled by its respective input/output control unit of the third group; and an assign table memory domain for storing address information to access the respective unit control word memory domains of the second and third groups.