PROCESSOR/SIGNALLING CIRCUIT INTERFACE WITH INTERMEDIATE QUANTISATION AND STORAGE

摘要

1524109 Data processing system INTERNATIONAL STANDARD ELECTRIC CORP 14 Dec 1976 [19 Dec 1975] 52109/76 Heading G4A [Also in Division H4] A signal transfer system between a central unit and a number of peripheral circuits includes a store for each circuit which stores a group of signal samples for a signalling event and a speed indication, a control means including a clock for controlling the transfer of samples between a storing device and a circuit and access means for asynchrous transfer of groups of samples between the storing devices and the central unit, the speed indication being used by the control means for transfer of individual samples from the storing device to the respective peripheral circuit at the appropriate speed. Fig. 2 shows the transfer from the circuits, e.g. line or junction circuits CC 1 to CC n to a central unit UC (not shown) and Fig. 5 from the central unit to the circuits. Each circuit CC is associated with a storage cell Cr in a memory MER. A scanner EXP scans the circuits and supplies signal samples to a reception logic circuit LER which also receives the stored information in the respective cell Cr; circuit LER under the control of a clock CKR updates the information in the store MER for each circuit in turn, by storing all the samples successively obtained from a circuit. The number of samples may be fixed or it may depend on the nature of the signal to be monitored but the speed is controlled by the stored indication. When the sampling for a particular circuit has finished, the group of samples is transferred to the central unit UC through an access circuit LAR, asynchronously. The central unit UC may access the circuits directly through the scanner EXP, via connections ecr1, nc, ic1. Transfer of information from the central unit UC to the circuits CC 1 to CCn is analogous; information from the central unit UC is transferred in groups, through an access circuit LAE to a store MEE and from the store, one sample at a time, through a circuit LEE and a distributor DTR to the circuits, CC 1 to CC n . Again, the central unit UC may access the circuits directly through the distributor DTR by connections aded and sed.