| 摘要 |
<p>An access control unit for controlling a memory device having a plurality of memory units for storing data in a manner whereby the memory units are accessed sequentially, comprises a data register for storing data read out from the memory device, a cycle designation device for indicating in every cycle the memory unit of the memory device to be accessed in the relevant cycle, an address device for providing in each cycle an address to the memory unit indicated by the cycle designation device, a non-coincidence detection circuit for detecting non-coincidence between the memory unit indicated by the address and the memory unit practically provided with that address, and an invalidating device utilizing the output of the non-coincidence detection circuit for invalidating data read out from the memory device in a cycle a specified number of cycles after that in which non-coincidence is detected.</p> |
