发明名称 |
FREQUENCY SHIFT DEMODULATOR HAVING A VARIABLE CLOCK RATE |
摘要 |
<p>Frequency-shift data signals, in particular those whose maximum data transmission rate is comparable to the carrier frequency, are accurately demodulated by digital means through the use of binary counters which are regularly reset by zero-crossing transitions in the received signals. An averaging counter arrangement driven by a free-running high-speed clock whose rate greatly exceeds the maximum data rate continuously computes the period of received signals. Counts corresponding to successive periods are transferred to a threshold counter arrangement which effectively counts up or down at further clock rates proportional to the periods of preselected mark and space frequencies toward predetermined threshold count levels which indicate transitions in the baseband data signals. The threshold counter arrangement need only count in one direction provided the counts from the averaging counter arrangement corresponding to the lower frequency-shift frequency are complemented before transfer to the threshold counter arrangement.</p> |
申请公布号 |
CA1033018(A) |
申请公布日期 |
1978.06.13 |
申请号 |
CA19740214950 |
申请日期 |
1974.11.29 |
申请人 |
WESTERN ELECTRIC COMPANY, INCORPORATED |
发明人 |
TONG, SHIH Y. |
分类号 |
H04L27/156;(IPC1-7):04L27/14 |
主分类号 |
H04L27/156 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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