| 发明名称 |
FAIL-SAFE ACTIVE TIMING CIRCUIT |
| 摘要 |
<p>A fail-safe timing circuit which includes a variable passive timing element and an active timer or timing device so as to control a device, for example, a fail-safe or B-relay such as is used in railroad signaling.</p> |
| 申请公布号 |
CA1033017(A) |
申请公布日期 |
1978.06.13 |
| 申请号 |
CA19750241055 |
申请日期 |
1975.12.04 |
| 申请人 |
GENERAL SIGNAL CORPORATION |
发明人 |
BUTLER, WILLIAM K.;ANDERSON, ROBERT F. |
| 分类号 |
B60L3/04;H03K3/023;H03K3/78;H03K17/28 |
主分类号 |
B60L3/04 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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